A simulator for at-speed robust testing of path delay faults in combinational circuits

被引：5
|
作者：
Hsu, YC
Gupta, SK
机构：
[1] Department of Electrical Engineering-Systems, University of Southern California, Los Angeles
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1996年 / 45卷 / 11期
基金：
美国国家科学基金会;
关键词：
delay testing; robust path delay testing; at-speed delay testing; fault simulation;
D O I：
10.1109/12.544489
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Conditions are derived for robust testing of a path delay fault via a sequence of vectors applied at-speed. A simulator has been developed that uses the above conditions, along with the knowledge of paths that are robustly tested by the previous vectors, to determine the fault coverage obtained by such testing. The results demonstrate the existing fault simulators can overestimate robust path delay fault coverage by 5-15%.
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页码：1312 / 1318
页数：7
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