High-Speed Grouping and Decomposition Multiplier for Binary Multiplication

In the computation systems that are frequently utilized in Digital Signal Processing (DSP)-and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence (R) Virtuoso and Cadence (R) Virtuoso Assura tools. From the front-end design of the 8 x 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power-delay product when compared to existing multiplier architectures. A further reduction in the power-delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.