A high-resolution time interpolator based on a delay locked loop and an RC delay line

被引：95

作者：

Mota, M ^{[1
]}

Christiansen, J

机构：

[1] High Energy Phys Lab, P-1000 Lisbon, Portugal

[2] CERN, European Ctr Particle Phys, CH-1211 Geneva 23, Switzerland

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 10期

关键词：

code density test; delay locked loop; high-resolution time measurement; RC delay line; time calibration; time to digital converter;

D O I：

10.1109/4.792603

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An architecture for a time interpolation circuit with an rms error of similar to 25 ps has been developed in a 0.7-mu m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT), The very small temperature/voltage dependence of R and C parameters and the self-calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.

引用

页码：1360 / 1366

页数：7

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