Power-Up Sequence Control for MTCMOS Designs

被引:9
作者
Chen, Shi-Hao [1 ,2 ]
Lin, Youn-Long [2 ]
Chao, Mango C. -T. [3 ,4 ]
机构
[1] Global Unichip Corp, Design Serv Div, Hsinchu 30078, Taiwan
[2] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu 30043, Taiwan
[3] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30010, Taiwan
[4] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30010, Taiwan
关键词
Dynamic IR; inrush current; low power design; multi-threshold CMOS (MTCMOS); power gating; power-up sequence; ramp-up time;
D O I
10.1109/TVLSI.2012.2187689
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Power gating is effective for reducing standby leakage power asmulti-thresholdCMOS(MTCMOS) designs have become popular in the industry. However, a large inrush current and dynamic IR drop may occur when a circuit domain is powered up with MTCMOS switches. This could in turn lead to improper circuit operation. We propose a novel framework for generating a proper power-up sequence of the switches to control the inrush current of a power-gated domain while minimizing the power-up time and reducing the dynamic IR drop of the active domains. We also propose a configurable domino-delay circuit for implementing the sequence. Experimental results based on state-of-the-art industrial designs demonstrate the effectiveness of the proposed framework in limiting the inrush current, minimizing the power-up time, and reducing the dynamic IR drop. Results further confirm the efficiency of the framework in handling large-scale designs with more than 80 K power switches and 100 M transistors.
引用
收藏
页码:413 / 423
页数:11
相关论文
共 22 条
[1]  
Anis M, 2002, DES AUT CON, P480, DOI 10.1109/DAC.2002.1012673
[2]  
[Anonymous], 2010, REDHAWK US MAN
[3]  
Cadence Design System Inc., 2011, ENC DIG IMPL SYST US, P491
[4]   Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits [J].
Calimera, Andrea ;
Benini, Luca ;
Macii, Alberto ;
Macii, Enrico ;
Poncino, Massimo .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (09) :1979-1993
[5]   DFM/DFY practices during physical designs for timing, signal integrity, and power [J].
Chen, Shi-Hao ;
Chu, Ke-Cheng ;
Lin, Jiing-Yuan ;
Tsai, Cheng-Hong .
PROCEEDINGS OF THE ASP-DAC 2007, 2007, :232-+
[6]   An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon [J].
Chen, Yu-Ting ;
Juan, Da-Cheng ;
Lee, Ming-Chao ;
Chang, Shih-Chieh .
IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, :779-782
[7]  
Davoodi A, 2005, ASIA S PACIF DES AUT, P868
[8]  
Hwang C, 2006, ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, P741
[9]  
Jiang HL, 2008, DES AUT CON, P980
[10]   Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits [J].
Jiao, Hailong ;
Kursun, Volkan .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (08) :2053-2065