共 22 条
[1]
Anis M, 2002, DES AUT CON, P480, DOI 10.1109/DAC.2002.1012673
[2]
[Anonymous], 2010, REDHAWK US MAN
[3]
Cadence Design System Inc., 2011, ENC DIG IMPL SYST US, P491
[5]
DFM/DFY practices during physical designs for timing, signal integrity, and power
[J].
PROCEEDINGS OF THE ASP-DAC 2007,
2007,
:232-+
[6]
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
[J].
IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2,
2007,
:779-782
[7]
Davoodi A, 2005, ASIA S PACIF DES AUT, P868
[8]
Hwang C, 2006, ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, P741
[9]
Jiang HL, 2008, DES AUT CON, P980