Wiring rule methodology for on-chip interconnects

被引：0
|
作者：
Smith, H
Cases, M
机构：
来源：
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING - IEEE 5TH TOPICAL MEETING | 1996年
关键词：
D O I：
10.1109/EPEP.1996.564769
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A wiring rule methodology which control line to line signal coupling and transition rate degradations are described. Technology trends are discussed and parametric curves presented which illuminate optimized wire geometries that are used to satisfy these electrical constraints for high wire density chips.
引用
收藏
页码：33 / 35
页数：3
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