A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs

In this brief, a power-efficient digital technique for gain and offset correction in slope analog-to-digital converters (ADCs) has been proposed. The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by a specially prepared clock-enable pulse sequence. This brief describes the properties of ADCs utilizing this clock stopping technique, including power dissipation, integral, and differential nonlinearity. The experimental validation has been performed for the ASIC implementation of the 128-pixel imager containing photo-sensors integrated with ADCs. Finally, a modification is proposed that increases the accuracy of the gain correction. Measurements confirm functionality of the proposed approach. Reduction of the PRNU (to similar to 0.4 LSB) has been achieved as well.