Demonstration of SiC Vertical Trench JFET Reliability

被引：1

作者：

Speer, Kevin M. ^{[1
]}

Chatty, Kiran ^{[1
]}

Bondarenko, Volodymyr ^{[1
]}

Sheridan, David C. ^{[1
]}

Matocha, Kevin ^{[1
]}

Casady, Jeffrey B. ^{[1
]}

机构：

[1] SemiS Labs, Starkville, MS 39759 USA

来源：

SILICON CARBIDE AND RELATED MATERIALS 2011, PTS 1 AND 2 | 2012年 / 717-720卷

关键词：

silicon carbide; JFET; transistor; reliability; dislocations; stacking faults; degradation; DEGRADATION; OPERATION;

D O I：

10.4028/www.scientific.net/MSF.717-720.1017

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device's intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.

引用

页码：1017 / 1020

页数：4

共 7 条

[1] A new degradation mechanism in high-voltage SiC power MOSFETs [J].