Programmable Clock Delay for Hysteresis Adjustment in Dynamic Comparators

The comparator hysteresis adjustment has allowed emerging new application fields including peak detectors and spectrum analyzers. However, hysteresis programming techniques has been mainly developed for static comparators. Hence, when high speed operation and reduced silicon area are desired, such techniques should also be developed for dynamic comparators. This paper presents a new hysteresis programming technique in dynamic comparators based on the digital programming of the clock delay. For this purpose and to ensure optimal circuit performance, a new delay circuit has been designed. To validate the design, a dynamic comparator with 4-bit hysteresis programming has been implemented and simulated using a commercially available 0.18 m CMOS process. The comparator hysteresis is then adjusted form 200 V to 17mV. The whole circuit consumes 1.1pJ at 500MHz while consuming less than 65 W of static power.