Real-Time FPGA Implementation of Range and Velocity Deception Techniques

被引:0
作者
Gunay, Osman [1 ]
Ergezer, Halit [1 ]
Ipek, Eyuphan [1 ]
Aras, Ekrem [1 ]
机构
[1] MIKES Mikrodalga Elekt Sistemler Sanayi & Ticaret, TR-06750 Ankara, Turkey
来源
2013 21ST SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE (SIU) | 2013年
关键词
Radar; Electronic Attack; Range Deception; Velocity Deception; FPGA;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a method that is developed for the simulation of range and velocity deception techniques on FPGAs is presented. The signal that will be received from environment by the radar, is modeled in baseband with the effects of the deception techniques. Range deception is modeled by changing the delay and Pulse Repetatition Intervals (PRI) of the radar signal according to the profile of the deception technique. Velocity deception technique is modeled by adjusting the phase of the baseband signal according to the doppler effect of the velocity difference that is calculated using the profile of the deception technique. Coordinated range and velocity deception is applied by synchronizing the profiles of both techniques. The method that is developed allows the generation of baseband radar signals on a Xilinx Virtex-5 FPGA at 200 MHz sampling frequency.
引用
收藏
页数:4
相关论文
共 5 条
[1]  
[Anonymous], 2001, EW 101 1 COURSE ELEC
[2]  
Jing Y., 2011, 4 INT C IM SIGN PROC, V4, P2177
[3]   Range gate pull off (RGPO): Detection, observability and alpha-beta target tracking [J].
Kalata, PR ;
Chmielewski, TA .
PROCEEDINGS OF THE TWENTY-NINTH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 1997, :505-508
[4]  
Schleher D., 1999, ARTECCH HOUSE RADAR
[5]  
Townsend J., 2008, THESIS AIR FORCE I T