Novel Nonvolatile L1/L2/L3 Cache Memory Hierarchy Using Nonvolatile-SRAM With Voltage-Induced Magnetization Switching and Ultra Low-Write-Energy MTJ

被引：15

作者：

Fujita, Shinobu ^{[1
]}

Noguchi, H. ^{[1
]}

Nomura, K. ^{[1
]}

Abe, K. ^{[1
]}

Kitagawa, E. ^{[1
]}

Shimomura, N. ^{[1
]}

Ito, J. ^{[1
]}

机构：

[1] Toshiba Co Ltd, Toshiba Corp R&D Ctr, Kawasaki, Kanagawa 2128582, Japan

来源：

IEEE TRANSACTIONS ON MAGNETICS | 2013年 / 49卷 / 07期

关键词：

Magnetic-tunneling-junction (MTJ); nonvolatile memory; nonvolatile cache memory; STT-MRAM; voltage-induced magnetization switching;

D O I：

10.1109/TMAG.2013.2245638

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To reduce power consumption of CPU, nonvolatile cache memory has been expected by replacing conventional volatile cache memory based on SRAM. This paper describes nonvolatile cache memory hierarchy design using fast and low-power perpendicular (FL-p-) STT-MRAM. For L3, L2 and L1 cache, 1T-1MTJ with FL-p-STT-MRAM, 6T-2MTJ, and short write pulse based 6T-2MTJ having voltage-induced magnetization switching has been presented for the most suitable combination for the cache memory.

引用

页码：4456 / 4459

页数：4

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