A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

被引：39

作者：

Nazemi, Ali ^{[1
]}

Grace, Carl ^{[1
]}

Lewyn, Lanny ^{[1
]}

Kobeissy, Bilal ^{[1
]}

Agazzi, Oscar ^{[1
]}

Voois, Paul ^{[1
]}

Abidin, Cindra ^{[1
]}

Eaton, George ^{[1
]}

Kargar, Mahyar ^{[1
]}

Marquez, Cesar ^{[1
]}

Ramprasad, Sumant ^{[1
]}

Bollo, Federico ^{[2
]}

Posse, Vladimir A. ^{[1
]}

Wang, Stephen ^{[1
]}

Asmanis, Georgios ^{[1
]}

机构：

[1] ClariPhy Commun Inc, 16 Technol Dr,Suite 165, Irvine, CA 92618 USA

[2] ClariPhy Argentina, Cordoba, Argentina

来源：

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2008年

关键词：

D O I：

10.1109/VLSIC.2008.4585935

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10.3GS/s ADC with 5GHz input BW and 6 bit resolution in 90nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6dB SNDR) for a 100MHz input signal and 5.1 ENOB (32.4dB SNDR) for a 5GHz input (Nyquist) with phase offset correction across the interleaved array.

引用

页码：18 / +

页数：2

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