A 16Gb/s/link, 64Gb/s bidirectional asymmetric memory interface cell

被引：6

作者：

Chang, Ken ^{[1
]}

Lee, Haechang ^{[1
]}

Chun, Jung-Hoon ^{[1
]}

Wu, Ting ^{[1
]}

Chin, T. J. ^{[1
]}

Kaviani, Kambiz ^{[1
]}

Shen, Jie ^{[1
]}

Shi, Xudong ^{[1
]}

Beyene, Wendem ^{[1
]}

Frans, Yohan ^{[1
]}

Leibowitz, Brian ^{[1
]}

Nguyen, Nhat ^{[1
]}

Quan, Fredy ^{[1
]}

Zerbe, Jared ^{[1
]}

Perego, Rich ^{[1
]}

Assaderaghi, Fari ^{[1
]}

机构：

[1] Rambus Inc, Los Altos, CA 94022 USA

来源：

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2008年

关键词：

D O I：

10.1109/VLSIC.2008.4585978

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An asymmetric memory interface cell with 32 bidirectional data and four unidirectional request links operating at 16Gb/s per link is implemented in TSMC 65nm CMOS process technology. Timing adjustment and equalization circuits for both memory read and write are on the controller to reduce the memory cost. Each link operates at a maximum rate of 16Gb/s with sufficient and comparable margins in both directions at a BER of 10(-12). The measured energy efficiency for the controller interface cell is 13mW/Gb/s under nominal operating conditions.

引用

页码：126 / 127

页数：2