共 43 条
- [31] High Speed and Memory Efficient VLSI Architecture of 2D 5/3 DWT Using Interlaced Scan Algorithm for JPEG2000 PROCEEDINGS OF 2012 2ND INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND NETWORK TECHNOLOGY (ICCSNT 2012), 2012, : 180 - 184
- [32] Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributed Arithmetic for 2D DTCWT Computation on FPGA INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2019, 49 (03): : 119 - 132
- [38] 2-D Joint High-Resolution ISAR Imaging With Random Missing Observations via Cyclic Displacement Decomposition-Based Efficient SBL IEEE TRANSACTIONS ON GEOSCIENCE AND REMOTE SENSING, 2024, 62
- [40] A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition Journal of Real-Time Image Processing, 2020, 17 : 1421 - 1446