共 43 条
- [21] A High-Speed 2-D IDCT Processor for Image/Video Decoding PROCEEDINGS OF THE 2009 2ND INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, VOLS 1-9, 2009, : 3494 - +
- [22] An Efficient High-Speed Lifting Based 1D/2D-DWT VLSI Architecture Using CDF-5/3 Wavelet Transform For Image Processing Applications 2020 5TH IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS ON ELECTRONICS, INFORMATION, COMMUNICATION & TECHNOLOGY (RTEICT-2020), 2020, : 269 - 274
- [23] An Internal Folded Hardware-Efficient Architecture for Lifting-Based Multi-Level 2-D 9/7 DWT APPLIED SCIENCES-BASEL, 2019, 9 (21):
- [24] Energy- and Area-Efficient Parameterized Lifting-Based 2-D DWT Architecture on FPGA 2014 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2014,
- [27] Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme Journal of Signal Processing Systems, 2010, 61 : 219 - 230
- [28] Comparative Analysis of Memory Efficient Hardware Architectures for Lifting Based and Non-Stationary Filter Based 5/3 2-D Inverse DWT 2019 8TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2019, : 188 - 191
- [29] Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2010, 61 (02): : 219 - 230