Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance

被引：38

作者：

Gili, E

Kunz, VD

de Groot, CH ^{[1
]}

Uchino, T

Ashburn, P

Donaghy, DC

Hall, S

Wang, Y

Hemment, PLF

机构：

[1] Univ Southampton, Dept Elect & Comp Sci, Southampton SO9 5NH, Hants, England

[2] Univ Liverpool, Dept Elect Engn & Elect, Liverpool L69 3BX, Merseyside, England

[3] Univ Surrey, Sch Elect Comp & Math, Guildford GU2 5XH, Surrey, England

来源：

SOLID-STATE ELECTRONICS | 2004年 / 48卷 / 04期

基金：

英国工程与自然科学研究理事会;

关键词：

vertical MOSFETs; parasitic capacitance; FILOX; surround gate; double gate;

D O I：

10.1016/j.sse.2003.09.019

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50 run. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel length down to 100 nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100 mV. The short channel effects of the surround gate MOSFETs are investigated. (C) 2003 Elsevier Ltd. All rights reserved.

引用

页码：511 / 519

页数：9