Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor

This study describes a low-power 16-bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 mu m complementary metal-oxide-semiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm(2). Simulation results with this architecture, using clock frequencies up to 100 MHz have confirmed results from other researchers that clocked adiabatic consumes up to ten times less power than conventional CMOS logic.