Implementation of a Fast and Low-Power Thermopile Readout Circuit Arrangement for Array Processors

High-speed thermal imaging is necessary in many applications. However, the traditional column-wise readout implementations reduce the achievable frame rate. Also, analog integration for each individual pixel is not possible without sacrificing pixel area. In this brief, we present an implementation of a fast and low-power pixel-wise readout circuit scheme with a digital integration method using 65-nm standard CMOS technology. The power consumption of the readout circuit is up to 15 mu W and the layout area is 100 mu m x 100 mu m. Furthermore, we analyze our design for non-idealities, such as noise and process mismatches using a circuit simulator.