We address RC scaling trends and predict the performance benefits of advanced metallization options with respect to conventional Cu/low-k interconnects. The range of interconnect dimensions we cover spans from the 22 nm to the 3 nm logic technology node. We show that Ru and Co fills can significantly reduce resistance at narrow pitches. At 12 nm half-pitch, line and via resistance can be lowered by up to 36% and 75%, respectively, by replacing Cu with barrierless Ru fill; by using hybrid Cu metallization with Co via-prefill, at 12 nm half-pitch via resistance can be lowered by up to 42% in 87 degrees tapered vias and up to 52% in chamfered vias. As far as capacitance is concerned, Ru fill can enable interconnect schemes without dielectric liner. In this case, the line capacitance can be substantially reduced by using linerless replacement low-k or air-gap schemes, whose benefits become more significant at narrow pitches, when one accounts for low-k sidewall damage in conventional low-k schemes and takes these as a reference.
