An implementation of area and power efficient digital FIR filter for hearing aid applications

Very Large Scale Integration (VLSI) implementations specifically for low power, area efficient, and Energy delay product in TSMC 90nm technology to test the necessity of giving 100% usefulness of the harmed human hearing devices. The linear phase finite impulse response (LPFIR) filter is utilized for low area and less power consumption. In LPFIR filter, the logic optimization relies on the accessibility of redundant operations in the detailing. However, multiplication and accumulation path logic optimized without giving any thought to the data dependence. The proposed digital FIR filter logic is dispensed all of the redundant logic operations of the LPFIR filter and logic optimized in the data dependence. Wallace tree multiplier, carry save multiplier, transmission gates multiplier, ripple carry multiplier and booth carry save multiplier also been approached for hearing aid. But Hybrid multiplier with modified conventional carry save adder is proposed in digital FIR filtering architecture. An area efficient and power consumed reconfigurable non-uniform computerized programmed digital finite impulse response (FIR) filter is utilized in the hearing aid application. The digital FIR filter is implemented in TSMC 90nm technology. The proposed multiplier gets less 285 logic cells, 1087 numbers of logic equivalents, 28000 mu m(2) area, 2.7W/Hz dynamic energy, 0.39nw static power, 95ns delay and 0.26Js energy delay product. The proposed method is covered 36798 logic gates and consumed 75.4 mu m power with 182.5ns delay.