Low-power low-leakage FPGA design using Zigzag power gating, dual-VTH/VDD and micro-VDD-hopping

A low-power FPGA design approach is proposed based on a fine-grain V-DD control scheme called micro-VDD-hopping. Four configurable logic blocks (CLBs) are grouped into one block where VFD is shared. In the micro-V-DD-hopping scheme, VFD in each block is changed between V-DDH (high VFD) and V-DDL (low VFD) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for low-swing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakage-path problem. A test chip was fabricated using a 0.35-mu m CMOS technology, together with the conventional fixed-V-DD FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%.