Implementation of the FFT butterfly with redundant arithmetic

被引:16
作者
Bruguera, JD [1 ]
Lang, T [1 ]
机构
[1] UNIV CALIF IRVINE,DEPT ELECT & COMP ENGN,IRVINE,CA 92717
来源
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1996年 / 43卷 / 10期
关键词
D O I
10.1109/82.539004
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present an architecture for the implementation of the radix-4 FFT butterfly with redundant arithmetic, based in the utilization of carry-save adders and a signed-digit representation of the multipliers in the multiplications. As the carry propagation is eliminated, a high throughput is maintained with a reduced hardware cost, when compared to other architectures based on carry-propagate additions.
引用
收藏
页码:717 / 723
页数:7
相关论文
共 15 条
[1]   LOW-POWER CMOS DIGITAL DESIGN [J].
CHANDRAKASAN, AP ;
SHENG, S ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484
[2]   CONCURRENT ERROR-DETECTABLE BUTTERFLY CHIP FOR REAL-TIME FFT PROCESSING THROUGH TIME REDUNDANCY [J].
CHEN, TH ;
CHEN, LG .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (05) :537-547
[3]  
Ercegovac M.D., 1994, Division and Square Root: Digit Recurrence Algorithms and Implementations
[4]  
Ghosh A., 1992, Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3), P253, DOI 10.1109/DAC.1992.227826
[5]  
GOMEZ S, 1988, ELECT ENG S, P99
[6]  
HOLLAND B, 1989, ELECTRON ENG, P29
[7]  
Hwang K., 1979, Computer Arithmetic-Principles, Architecture And Design
[8]  
MIYANAGA H, 1991, P IEEE INT C AC SPEE, P1193
[9]   A 15-NS 32X32-B CMOS MULTIPLIER WITH AN IMPROVED PARALLEL STRUCTURE [J].
NAGAMATSU, M ;
TANAKA, S ;
MORI, J ;
HIRANO, K ;
NOGUCHI, T ;
HATANAKA, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (02) :494-497
[10]   AN INTEGRATED MULTIPLIER FOR COMPLEX NUMBERS [J].
OKLOBDZIJA, VG ;
VILLEGER, D ;
SOULAS, T .
JOURNAL OF VLSI SIGNAL PROCESSING, 1994, 7 (03) :213-222