Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

被引：10

作者：

Eneman, G. ^{[1
,2
,3
]}

Hellings, G. ^{[1
,2
,4
]}

Mitard, J. ^{[1
]}

Witters, L. ^{[1
]}

Yamaguchi, S. ^{[5
]}

Bardon, M. Garcia ^{[1
]}

Christie, P. ^{[1
]}

Ortolland, C. ^{[6
]}

Hikavyy, A. ^{[1
]}

Favia, P. ^{[1
]}

Gonzalez, M. Bargallo ^{[1
,2
]}

Simoen, E. ^{[1
]}

Crupi, F. ^{[7
]}

Kobayashi, M. ^{[6
]}

Franco, J. ^{[1
,2
]}

Takeoka, S. ^{[8
]}

Krom, R. ^{[1
,2
]}

Bender, H. ^{[1
]}

Loo, R. ^{[1
]}

Claeys, C. ^{[1
,2
]}

De Meyer, K. ^{[1
,2
]}

Hoffmann, T. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium

[2] Katholieke Univ Leuven, ESAT INSYS Dept, B-3000 Louvain, Belgium

[3] Fund Sci Res Flanders FWO, B-1000 Brussels, Belgium

[4] IWT Vlaanderen, B-1000 Brussels, Belgium

[5] IMEC, Sony Assignee, B-3001 Louvain, Belgium

[6] IBM Corp, Armonk, NY 10504 USA

[7] Univ Calabaria, Arcavacata Di Rende, Italy

[8] IMEC, Panasonic Assignee, B-3001 Louvain, Belgium

来源：

DIELECTRICS IN NANOSYSTEMS -AND- GRAPHENE, GE/III-V, NANOWIRES AND EMERGING MATERIALS FOR POST-CMOS APPLICATIONS 3 | 2011年 / 35卷 / 03期

关键词：

D O I：

10.1149/1.3569940

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Si1-xGex-channel pFETs can combine enhanced intrinsic performance with a threshold voltage shift, therefore this technology possibly facilitates the use of high-k/metal gate stacks in high-performance applications. This review presents imec's work on a new device concept using Si1-xGex-channels, the implant-free quantum well transistor, that can additionally provide improved short-channel scalability, as well as further performance enhancement when compared to conventional silicon and Si1-xGex-channel pFETs. Furthermore, circuit simulations of Si1-xGex-channel pFETs indicate that this technology shows even more enhanced potential at reduced supply voltages, and also in circuits that allow operation at lower electric fields such as stacked transistors. Finally it is demonstrated that the layout sensitivity of Si1-xGex-channel pFETs is an important concern, especially for variations of the device width. The effectiveness of another stress technique, Si1-xGex Source/Drain, is shown to be decreased when used in combination with Si1-xGex-channel pFETs.

引用

页码：493 / 503

页数：11

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