A 0.18-μm CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

被引:32
|
作者
Song, Bongsub [1 ]
Kim, Kyunghoon [1 ]
Lee, Junan [1 ]
Burm, Jinwook [1 ]
机构
[1] Sogang Univ, Dept Elect Engn, Seoul 121742, South Korea
关键词
CMOS; currentmode logic (CML); high-speed integrated circuits; pulse-amplitude modulation (PAM); serial link; transceiver; DESIGN; PREEMPHASIS; EQUALIZER;
D O I
10.1109/TCSI.2012.2215799
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 0.18-mu m CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM technique, the dual-mode 10-PAM technique can reduce power dissipation by 62.5%. The transmitter including a pseudo random bit sequence (PRBS) generator, multiplexers, an encoder, and an output driver achieves 10-Gb/s data-rate with 235-mW power dissipation such that the figure of merit (FOM) of the transmitter part is 23.5 mW/(Gb/s). The receiver including a flash type analog-to-digital converter (ADC), a decoder, and output drivers achieves 10-Gb/s data-rate and 10(-12) BER with 190-mW power dissipation such that FOM of the receiver part is 19 mW/(Gb/s). The proposed 10-PAM transceiver was implemented in a 0.18-mu m standard CMOS technology with 0.3 0.8-mm(2) active area.
引用
收藏
页码:457 / 468
页数:12
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