Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2

被引:19
作者
Sun, Zheng [1 ,2 ]
Pang, Chin-Sheng [1 ,2 ]
Wu, Peng [1 ,2 ]
Hung, Terry Y. T. [3 ]
Li, Ming-Yang [3 ]
Liew, San Lin [4 ]
Cheng, Chao-Ching [3 ]
Wang, Han [3 ]
Wong, H-S Philip [3 ]
Li, Lain-Jong [3 ]
Radu, Iuliana [3 ]
Chen, Zhihong [1 ,2 ]
Appenzeller, Joerg [1 ,2 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
[2] Purdue Univ, Birck Nanotechnol Ctr, W Lafayette, IN 47907 USA
[3] Taiwan Semicond Mfg Co, Corp Res, Hsinchu 30075, Taiwan
[4] Taiwan Semicond Mfg Co, Qual & Reliabil, Hsinchu 30075, Taiwan
关键词
Monolayer TMD materials; WS2; field-effect transistors; statistical study; ultrascaled dielectric; ultrashort channel length; MOS2; TRANSISTORS; CONTACTS; RESISTANCE;
D O I
10.1021/acsnano.2c05902
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
Scaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS, FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.
引用
收藏
页码:14942 / 14950
页数:9
相关论文
共 53 条
  • [1] [Anonymous], 2020, International Roadmap for Devices and Systems Beyond CMOS
  • [2] Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab
    Asselberghs, I
    Smets, Q.
    Schram, T.
    Groven, B.
    Verreck, D.
    Afzalian, A.
    Arutchelvan, G.
    Gaur, A.
    Cott, D.
    Maurice, T.
    Brems, S.
    Kennes, K.
    Phommahaxay, A.
    Dupuy, E.
    Radisic, D.
    De Marneffe, J-F
    Thiam, A.
    Li, W.
    Devriendt, K.
    Huyghebaert, C.
    Lin, D.
    Caymax, M.
    Morin, P.
    Radu, I. P.
    [J]. 2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
  • [3] Bao WZ, 2009, NAT NANOTECHNOL, V4, P562, DOI [10.1038/nnano.2009.191, 10.1038/NNANO.2009.191]
  • [4] Lowering the Schottky Barrier Height by Graphene/Ag Electrodes for High-Mobility MoS2 Field-Effect Transistors
    Chee, Sang-Soo
    Seo, Dongpyo
    Kim, Hanggyu
    Jang, Hanbyeol
    Lee, Seungmin
    Moon, Seung Pil
    Lee, Kyu Hyoung
    Kim, Sung Wng
    Choi, Hyunyong
    Ham, Moon-Ho
    [J]. ADVANCED MATERIALS, 2019, 31 (02)
  • [5] Metal-Guided Selective Growth of 2D Materials: Demonstration of a Bottom-Up CMOS Inverter
    Chiu, Ming-Hui
    Tang, Hao-Ling
    Tseng, Chien-Chih
    Han, Yimo
    Aljarb, Areej
    Huang, Jing-Kai
    Wan, Yi
    Fu, Jui-Han
    Zhang, Xixiang
    Chang, Wen-Hao
    Muller, David A.
    Takenobu, Taishi
    Tung, Vincent
    Li, Lain-Jong
    [J]. ADVANCED MATERIALS, 2019, 31 (18)
  • [6] Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2D Electronics
    Chou, Ang-Sheng
    Wu, Tong
    Cheng, Chao-Ching
    Zhan, Shun-Siang
    Ni, I-Chih
    Wang, Shih-Yun
    Chang, Yu-Chen
    Liew, San-Lin
    Chen, Edward
    Chang, Wen-Hao
    Wu, Chih-, I
    Cai, Jin
    Wong, H-S Philip
    Wang, Han
    [J]. 2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
  • [7] High On-State Current in Chemical Vapor Deposited Monolayer MoS2 nFETs With Sn Ohmic Contacts
    Chou, Ang-Sheng
    Cheng, Chao-Ching
    Liew, San-Lin
    Ho, Po-Hsun
    Wang, Shih-Yun
    Chang, Yu-Chen
    Chang, Che-Kang
    Su, Yuan-Chun
    Huang, Zheng-Da
    Fu, Fang-Yu
    Hsu, Chen-Feng
    Chung, Yun-Yan
    Chang, Wen-Hao
    Li, Lain-Jong
    Wu, Chih-, I
    [J]. IEEE ELECTRON DEVICE LETTERS, 2021, 42 (02) : 272 - 275
  • [8] Role of Artificial Intelligence, Clinicians & Policymakers in Clinical Decision Making: A Systems Viewpoint
    Choudhury, Avishek
    Asan, Onur
    Mansouri, Mo
    [J]. 2019 5TH IEEE INTERNATIONAL SYMPOSIUM ON SYSTEMS ENGINEERING (IEEE ISSE 2019), 2019,
  • [9] Low-Resistance 2D/2D Ohmic Contacts: A Universal Approach to High-Performance WSe2, MoS2, and MoSe2 Transistors
    Chuang, Hsun-Jen
    Chamlagain, Bhim
    Koehler, Michael
    Perera, Meeghage Madusanka
    Yan, Jiaqiang
    Mandrus, David
    Tomanek, David
    Zhou, Zhixian
    [J]. NANO LETTERS, 2016, 16 (03) : 1896 - 1902
  • [10] Low-Temperature Ohmic Contact to Monolayer MoS2 by van der Waals Bonded Co/h-BN Electrodes
    Cui, Xu
    Shih, En-Min
    Jauregui, Luis A.
    Chae, Sang Hoon
    Kim, Young Duck
    Li, Baichang
    Seo, Dongjea
    Pistunova, Kateryna
    Yin, Jun
    Park, Ji-Hoon
    Choi, Heon-Jin
    Lee, Young Hee
    Watanabe, Kenji
    Taniguchi, Takashi
    Kim, Philip
    Dean, Cory R.
    Hone, James C.
    [J]. NANO LETTERS, 2017, 17 (08) : 4781 - 4786