THE IMPLEMENTATION OF CHANNELIZED RECEIVER THROUGH FPGA

被引：0

作者：

Huang Xiaohong ^{[1
]}

Xu Xianyin ^{[1
]}

机构：

[1] Hebei Polytech Univ, Coll Informat Engn, Tangshan 063000, Peoples R China

来源：

FIFTH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTER THEORY AND ENGINEERING (ICACTE 2012) | 2012年

关键词：

Channelization; polyphase filter; FPGA;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

The channelized receiver is obtained by polyphase filter banks, which makes Multi-channel signals received parallel. The channelizing is realized in the FPGA device of xc4vsx55 which belongs to Virtex4 group in Xilinx family. During the process of design, highly effective of polyphase and the parallel assembly line structure's FFT flexibility are fully considered, which reduce the operand enormously and raise the operating speed. Simulation is gotten by using combined simulation of ISE, Modelsim and Matlab, the result is confirmed effective.

引用

页码：809 / 816

页数：8

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