Controller-Embeddable Probabilistic Real-Time Digital Twins for Power Electronic Converter Diagnostics

被引:126
作者
Milton, Matthew [1 ]
De La O, Castulo [1 ]
Ginn, Herbert L. [1 ]
Benigni, Andrea [2 ,3 ]
机构
[1] Univ South Carolina, Dept Elect Engn, Columbia, SC 29208 USA
[2] Rhein Westfal TH Aachen, Chair Methods Simulating Energy Syst, D-52062 Aachen, Germany
[3] Forschungszentrum Juelich GmbH, Inst Energy Syst Engn, D-52428 Julich, Germany
关键词
Diagnostics; digital twin (DT); polynomial chaos; Power electronics; power system simulation; probabilistic logic; real-time systems; POLYNOMIAL-CHAOS; SIMULATION; PLATFORM;
D O I
10.1109/TPEL.2020.2971775
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this article, an approach is proposed for the online diagnostic analysis of power electronic converters utilizing real-time, probabilistic digital twinning. Under this approach, a digital twin (DT) of a power converter is defined as a real-time, probabilistic simulation model with stochastic (random) variables, developed using generalized polynomial chaos expansion. The DT models are partitioned in perspective of control layers for power converter subsystems in the approach, with emphasis on the application and converter control layers. Real-time executed solvers of these divided probabilistic DT models are embedded into power converter controllers running on field programmable gate array (FPGA) computing devices. Using a monitoring system, the real-time probabilistic DTs at each control layer and the corresponding physical twins of the power converter are compared by the controllers to determine if the power converter is operating within probable behavior. Knowing the large computational cost of probabilistic modeling, the resource usage and timing of real-time DT solvers on modern FPGAs is reported for common power electronic converter topologies, showing the approach is feasible and able to perform probabilistic real-time simulation of smaller power converters in perspective of application and converter control layers using <= 2 mu s time steps, with as lowas 70 ns steps; while staying embeddable within FPGA-based controllers. To highlight the capabilities of the proposed approach, a case study is presented using a probabilistic DT in the application layer controller of a pair of converters to comparatively monitor their behavior and corresponding controller action under hardware-in-the-loop testing.
引用
收藏
页码:9850 / 9864
页数:15
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