Design optimization of vertical double-gate tunneling field-effect transistors

被引：6

作者：

Yoon, Young Jun ^{[1
]}

Woo, Sung Yun ^{[1
]}

Seo, Jae Hwa ^{[1
]}

Lee, Jae Sung ^{[2
]}

Park, Yun Soo ^{[2
]}

Lee, Jung-Hee ^{[1
,2
]}

Kang, In Man ^{[1
,2
]}

机构：

[1] Kyungpook Natl Univ, Sch Elect Engn, Taegu 702701, South Korea

[2] Kyungpook Natl Univ, Sch Elect Engn & Comp Sci, Taegu 702701, South Korea

来源：

JOURNAL OF THE KOREAN PHYSICAL SOCIETY | 2012年 / 61卷 / 10期

基金：

新加坡国家研究基金会;

关键词：

Band-to-band tunneling; Double gate (DG); High-k dielectric; n-doped layer; Tunnel field-effect transistor; SIMULATION;

D O I：

10.3938/jkps.61.1679

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

In this work, design optimization of vertical double-gate (VDG) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials has been performed. High-k materials such as Si3N4, HfO2, and ZrO2 were used for the HG structure. The optimized parameters for maximizing the device performances were the length of the high-k material (Lhigh-k ) and the thickness of silicon channel (t (Si) ). For HfO2, the subthreshold swing (SS) and on-current were optimized at a Lhigh-k of 11 nm and a t (Si) of 5 nm. The optimized device had an on-current (I (on) ) of 151 A mu A/A mu m and a SS of 46.6 mV/dec. In addition, to improve the on-current level of the optimized device, we inserted a thin n-doped layer into the channel near the source side, and we analyzed the performance. The on-current level of the device with an n-doped layer was nearly double that of the device without an n-doped layer.

引用

页码：1679 / 1682

页数：4

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