A clock synchronization method for EtherCAT master

被引:13
作者
Chen, Xin [1 ]
Li, Di [1 ]
Wan, Jiafu [1 ]
Zhou, Nan [1 ]
机构
[1] South China Univ Technol, Sch Mech & Automot Engn, Guangzhou, Guangdong, Peoples R China
基金
中国国家自然科学基金;
关键词
EtherCAT; Clock synchronization; Packet loss;
D O I
10.1016/j.micpro.2016.03.002
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
EtherCAT has been widely applied in the motion control domain due to its advantages of the fast response speed, low CPU usage and good synchronization performance. Although the built-in distributed clock (DC) synchronization mechanism exhibits strong performance between slaves, the method of clock synchronization between the master and the reference clock is left open for selection by users and there are very few studies in this area. This paper introduces three synchronization modes for EtherCAT and analyzes the reasons for packet loss in free run mode and DC mode. This paper presents a novel method to realize the master clock synchronization with the reference clock. The proposed method can eliminate the settling time which is unusual in other synchronization mechanisms. The method is implemented on Windows with real-time extension and experimental results prove its feasibility. (C) 2016 Elsevier B.V. All rights reserved.
引用
收藏
页码:211 / 218
页数:8
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