A SmartBIST variant with guaranteed encoding

被引：206

作者：

Koenemann, B ^{[1
]}

Barnhart, C ^{[1
]}

Keller, B ^{[1
]}

Snethen, T ^{[1
]}

Farnsworth, O ^{[1
]}

Wheater, D ^{[1
]}

机构：

[1] IBM Microelect, San Jose, CA USA

来源：

10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ATS.2001.990304

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

SmartBIST is a name for a family of streaming scan test pattern decoders that are suitable for on -chip integration. The Automatic Test Pattern Generation (ATPG) algorithms are modified to generate scan test stimulus vectors in a highly compacted source format that is compatible with the SmartBIST decoder hardware. The compacted stimulus vectors are streamed from Automatic Test Equipment (ATE) to the decoder, which expands the data stream in real -time into fully expanded scan test vectors. SmartBIST encoding and decoding use simple algebraic techniques similar to those used for LFSR -Coding (also known as LFSR-Reseeding). The specific SmartBIST implementation shown in this paper guarantees that all test cubes can be successfully encoded by the modified ATPG algorithm irrespective of the number and position of the care bits.

引用

页码：325 / 330

页数：6

共 14 条

[1]

AKERS SB, 1985, P 15 INT S FAULT TOL, P148

[2]

[Anonymous], 1999, PROC INT TEST CONF

[3]

Bardell P. H., 1987, BUILT IN TEST VLSI P

[4]

BARNHART C, UNPUB ITC 01

[5]

BAYRAKTAROGLU, UNPUB DAC 01

[6]

DIEBOLD U, 1995, Patent No. 00481097

[7]

FARNSWORTH O, UNPUB ITC 01

[8] Reducing test application time for full scan embedded cores [J].

Hamzaoglu, I ;

Patel, JH .

TWENTY-NINTH ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, DIGEST OF PAPERS, 1999, :260-267

[9] Controllable LFSR for BIST [J].

Kay, D ;

Mourad, S .

IMTC/2000: PROCEEDINGS OF THE 17TH IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE: SMART CONNECTIVITY: INTEGRATING MEASUREMENT AND CONTROL, 2000, :223-228

[10]

KOENEMANN B, UNPUB TECS 01

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