Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms

被引:70
作者
Bhat, Ganapati [1 ]
Singla, Gaurav [2 ,3 ]
Unver, Ali K. [4 ]
Ogras, Umit Y. [1 ]
机构
[1] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85287 USA
[2] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85287 USA
[3] ARM Holdings, San Jose, CA 95134 USA
[4] Intel Corp, Assembly & Test Technol Dev, Chandler, AZ 85226 USA
基金
美国国家科学基金会;
关键词
Dynamic power management; heterogeneous computing; multicore architectures; multiprocessor systems-on-chip (MPSoCs); thermal management; PERFORMANCE; DESIGN;
D O I
10.1109/TVLSI.2017.2770163
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
State-of-the-art mobile platforms are powered by heterogeneous system-on-chips that integrate multiple CPU cores, a GPU, and many specialized processors. Competitive performance on these platforms comes at the expense of increased power density due to their small form factor. Consequently, the skin temperature, which can degrade the experience, becomes a limiting factor. Since using a fan is not a viable solution for hand-held devices, there is a strong need for dynamic thermal and power management (DTPM) algorithms that can regulate temperature with minimal performance impact. This paper presents a DTPM algorithm, which uses a practical temperature prediction methodology based on system identification. The proposed algorithm dynamically computes a power budget using the predicted temperature. This budget is used to throttle the frequency and number of cores to avoid temperature violations with minimal impact on the system performance. Our experimental measurements on two different octa-core big. LITTLE processors and common Android applications demonstrate that the proposed technique predicts the temperature with less than 5% error across all benchmarks. Using this prediction, the proposed DTPM algorithm successfully regulates the maximum temperature and decreases the temperature violations by one order of magnitude while also reducing the total power consumption on average by 7% compared with the default solution.
引用
收藏
页码:544 / 557
页数:14
相关论文
共 52 条
[1]  
[Anonymous], 2009, FUNDAMENTALS MODERN, DOI DOI 10.1017/CBO9781139195065
[2]  
Ayoub Raid, 2011, 2011 International Symposium on Low Power Electronics and Design (ISLPED 2011), P321, DOI 10.1109/ISLPED.2011.5993657
[3]  
Benini L., 2012, Dynamic power management: design techniques and CAD tools
[4]  
Bhat G., 2017, ACM T EMBED COMPUT S, V16
[5]   The PARSEC Benchmark Suite: Characterization and Architectural Implications [J].
Bienia, Christian ;
Kumar, Sanjeev ;
Singh, Jaswinder Pal ;
Li, Kai .
PACT'08: PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 2008, :72-81
[6]  
Bogdan P., 2012, 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), P35, DOI 10.1109/NOCS.2012.32
[7]  
Boyd L., 2004, CONVEX OPTIMIZATION
[8]   Dynamic thermal management for high-performance microprocessors [J].
Brooks, D ;
Martonosi, M .
HPCA: SEVENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTING ARCHITECTURE, PROCEEDINGS, 2001, :171-182
[9]   Power, thermal, and reliability modeling in nanometer-scale microprocessors [J].
Brooks, David ;
Dick, Robert P. ;
Joseph, Russ ;
Shang, Li .
IEEE MICRO, 2007, 27 (03) :49-62
[10]  
Chandrakasan A.P., 2000, Design of high-performance microprocessor circuits