Characterization of a Single-Supply Subthreshold FPGA

This paper presents a pair of field programmable gate array (FPGA) test chips optimized for subthreshold operation to maximize energy efficiency. Both chips were fabricated in the IBM 0.18 mu m silicon-on-insulator (SOI) process using the same FPGA architecture; one making use of conventional static CMOS multiplexers and one using dynamic threshold MOS (DTMOS) multiplexers. Reliable subthreshold operation is achieved for both test chips by replacing conventional SRAM with variation-tolerant interruptible latches. For the chip with conventional multiplexers, testing across eleven dice showed an average minimum operating voltage of 300 mV. A 43X reduction in power delay product (PDP) was seen compared to 1.5V operation. For the DTMOS chip, testing across four dice showed an average minimum operating voltage of 260 mV. The test results show that the DTMOS chip is more reliable at sub-300 mV, consistent with simulations. Minimum energy analysis of both test chips suggests that the minimum energy point for the FPGA occurs at subthreshold voltages.