MOSFET design for forward body biasing scheme

被引：30

作者：

Hokazono, Akira ^{[1
]}

Balasubramanian, Sriram

Ishimaru, Kazunari

Ishiuchi, Hidemi

Liu, Tsu-Jae King

Hu, Chenming

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

[2] Toshiba Co Ltd, Semicond Co, SoC Res & Dev Ctr, Isogo Ku, Yokohama, Kanagawa 358522, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 2006年 / 27卷 / 05期

关键词：

body bias; forward bias; MOSFET; reverse bias; substrate bias; work function;

D O I：

10.1109/LED.2006.873382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body bias is experimentally evaluated for devices with various channel-doping profiles to provide guidance for channel engineering in a forward body-biasing scheme. Furthermore, simulations of 10-nm-gate CMOS (hp22-nm node) devices are performed to study the optimal channel-doping profile and gate work function engineering for a forward biasing scheme.

引用

页码：387 / 389

页数：3

共 7 条

[1] Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI [J].

Assaderaghi, F ;

Sinitsky, D ;

Parke, SA ;

Bokor, J ;

Ko, PK ;

Hu, CM .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (03) :414-422

[2] Circuit techniques for subthreshold leakage avoidance, control, and tolerance [J].

Borkar, S .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :421-424

[3] HOT-ELECTRON-INDUCED MOSFET DEGRADATION - MODEL, MONITOR, AND IMPROVEMENT [J].

HU, CM ;

TAM, SC ;

HSU, FC ;

KO, PK ;

CHAN, TY ;

TERRILL, KW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) :375-385

[4] Scalability and biasing strategy for CMOS with active well bias [J].

Huang, SF ;

Wann, C ;

Huang, WS ;

Lin, CY ;

Schafbauer, T ;

Cheng, SM ;

Cheng, YC ;

Vietzike, D ;

Eller, M ;

Lin, C ;

Ye, QY ;

Rovedo, N ;

Biesemans, S ;

Nguyen, P ;

Dennard, R ;

Chen, BM .

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, :107-108

[5]

Kimizuka N, 2005, 2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P218

[6] Optimum conditions of body effect factor and substrate bias in variable threshold voltage MOSFETs [J].

Koura, H ;

Takamiya, M ;

Hiramoto, T .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2000, 39 (4B) :2312-2317

[7]

Togo M, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P88

← 1 →