Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA

被引：5

作者：

Grossmann, Peter J. ^{[1
,2
]}

Leeser, Miriam E. ^{[3
]}

Onabajo, Marvin ^{[3
]}

机构：

[1] MIT Lincoln Lab, Lexington, MA 02420 USA

[2] Northeastern Univ, Boston, MA 02115 USA

[3] Northeastern Univ, Elect & Comp Engn Dept, Boston, MA 02115 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2012年 / 59卷 / 12期

关键词：

Field-programmable gate array (FPGA); low-power design; minimum energy operation; power-delay product; subthreshold FPGA; variation-aware design; DESIGN;

D O I：

10.1109/TCSII.2012.2231035

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Field-programmable gate arrays (FPGAs) are an attractive option for low-power systems requiring flexible computing resources. However, the lowest power systems have yet to adopt FPGAs. Subthreshold circuit operation offers the opportunity to operate FPGAs at their minimum energy point. This paper presents data measured from an FPGA test chip fabricated in a 0.18-mu m SOI process. It is shown that the test chip can function at supply voltages as low as 0.26 V without an extra supply for write assists by using latches for configuration bit storage instead of static random access memory. Investigation of the minimum energy point of the FPGA for a high-activity test pattern shows that the minimum energy point of the FPGA can be well below the threshold voltage of the transistors.

引用

页码：942 / 946

页数：5