Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA

Field-programmable gate arrays (FPGAs) are an attractive option for low-power systems requiring flexible computing resources. However, the lowest power systems have yet to adopt FPGAs. Subthreshold circuit operation offers the opportunity to operate FPGAs at their minimum energy point. This paper presents data measured from an FPGA test chip fabricated in a 0.18-mu m SOI process. It is shown that the test chip can function at supply voltages as low as 0.26 V without an extra supply for write assists by using latches for configuration bit storage instead of static random access memory. Investigation of the minimum energy point of the FPGA for a high-activity test pattern shows that the minimum energy point of the FPGA can be well below the threshold voltage of the transistors.