An improved method about AES and FPGA high-speed realize

It is difficult to design to generate a S box with excellent crytographic properties in AES algorithms. So Wu Wenling et al. proposed a new S box. The paper is based on the new S box to realize extension from one set to multiple sets of S boxes by utilizing S box to generate time-shift selection function. And employ the dynamic S box of encryption and decryption scheme to AES advanced encryption algorithm. Then, design the S box on the FPGA platform. The simulation confirms that the method improves the speed of the encryption algorithm and reduces hardware logic unites of the encryption algorithm.