A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC NOR Flash Memories

被引：13
作者：
Wang Xueqiang [1 ]
Pan Liyang [1 ,2 ]
Wu Dong [1 ,2 ]
Hu Chaohong [3 ]
Zhou Runde [1 ,2 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Tsinghua Natl Lab Informat Sci & Technol, Beijing 100084, Peoples R China
[3] Intel Technol Dev Shanghai Co Ltd, Shanghai 200131, Peoples R China
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2009年 / 56卷 / 11期
关键词：
Error-correcting code (ECC); fast-decoding algorithm; multilevel-cell (MLC) NOR flash memories; two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder;
D O I：
10.1109/TCSII.2009.2029144
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in NOR flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of NOR flash memories.
引用
收藏
页码：865 / 869
页数：5
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