On-chip segmented bus: A self-timed approach

Bus structure is one of the important issues within the present day system-on-chip design paradigm. Speed and power consumption characteristics of a bus-based device are highly dependent on the bus organization. We propose a segmented bus architecture which shows potential for improving both speed and power related figures of a bus-based system. From a globally asynchronous locally synchronous systems perspective, self-timed logic seems appropriate for interconnecting sub-systems operating at different speeds. Hence, inter-module control follows self-timed design rules, whereas modules themselves can be synchronous entities.