Field programmable gate array based parallel matrix multiplier for 3D affine transformations

被引:3
作者
Bensaali, F.
Amira, A.
机构
[1] Univ Hertfordshire, Sch Elect Commun & Elect Engn, Hatfield AL10 9AB, Herts, England
[2] Brunel Univ, Sch Engn & Design, Uxbridge UB8 3PH, Middx, England
来源
IEE PROCEEDINGS-VISION IMAGE AND SIGNAL PROCESSING | 2006年 / 153卷 / 06期
关键词
D O I
10.1049/ip-vis:20045076
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, computer aided design or visualisation applications. This article investigates the suitability of field programmable gate array devices as an accelerator for implementing 3D affine transformations. Proposed solution based on processing large matrix multiplication have been implemented, for large 3D models, on the RC1000 Celoxica board based development platform using Handel-C. Outstanding results have been obtained for the acceleration of 3D transformations using fixed and floating-point arithmetic.
引用
收藏
页码:739 / 746
页数:8
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