N-Dimensional Twin Torus Topology

被引:12
作者
Andujar-Munoz, Francisco J. [1 ]
Villar-Ortiz, Juan A. [1 ]
Sanchez, Jose L. [1 ]
Jose Alfaro, Francisco [1 ]
Duato, Jose [2 ]
机构
[1] Univ Castilla La Mancha, Dept Comp Syst, Albacete, Spain
[2] Univ Politecn Valencia, Dept Syst Data Proc & Comp, Valencia, Spain
关键词
Interconnection network; torus topology; switch architecture; formal analysis; performance evaluation;
D O I
10.1109/TC.2014.2378267
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Torus topology is one of the preferred topologies for the interconnection network in high-performance clusters and supercomputers. Cost and scalability are some of the properties that make torus suitable for systems with a large number of nodes. The 3D torus is the version more extended due to its excellent nearest neighbor. However, some of the last supercomputers have been built using a torus network with five or six dimensions. To obtain an nD torus, 2n ports per node are needed, which can be offered by a single or several cards per node. In the second case, there are multiple ways of assigning the dimension and direction of the card ports. In previous work we defined and characterized the 3D Twin (3DT) torus which uses two four-port cards per node. In this paper we extend that previous work to define the n-dimensional Twin (nDT) torus topology. In this case, we formally obtain the optimal port configuration when (n + 1)-port cards are used instead of 2n-port cards. Moreover, we explain how deadlock problem can appear and propose a simple solution. Finally, we include evaluation results which show performance increases when an nDT torus is used instead of an nD torus with fewer dimensions and with the same computational resources.
引用
收藏
页码:2847 / 2861
页数:15
相关论文
共 21 条
[1]  
Ajima Y., 2011, Proceedings of the 2011 IEEE 19th Annual Symposium on High-Performance Interconnects (HOTI 2011), P87, DOI 10.1109/HOTI.2011.21
[2]  
Alverson Robert, 2010, Proceedings of the 18th IEEE Symposium on High Performance Interconnects (HOTI 2010), P83, DOI 10.1109/HOTI.2010.23
[3]   HIGH-SPEED SWITCH SCHEDULING FOR LOCAL-AREA NETWORKS [J].
ANDERSON, TE ;
OWICKI, SS ;
SAXE, JB ;
THACKER, CP .
ACM TRANSACTIONS ON COMPUTER SYSTEMS, 1993, 11 (04) :319-352
[4]   Building 3D Torus Using Low-Profile Expansion Cards [J].
Andujar, Francisco J. ;
Villar, Juan A. ;
Sanchez, Jose L. ;
Alfaro, Francisco J. ;
Duato, Jose .
IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (11) :2701-2715
[5]  
[Anonymous], 2002, 2002 ACMIEEE C SUPER, P1, DOI DOI 10.1109/SC.2002.10017
[6]  
Bossard Antoine, 2013, Algorithms and Architectures for Parallel Processing. 13th International Conference, ICA3PP 2013. Proceedings: LNCS 8286, P11, DOI 10.1007/978-3-319-03889-6_2
[7]   A flow control mechanism to avoid message deadlock in k-ary n-cube networks [J].
Carrion, C ;
Beivide, R ;
Gregorio, JA ;
Vallejo, F .
FOURTH INTERNATIONAL CONFERENCE ON HIGH-PERFORMANCE COMPUTING, PROCEEDINGS, 1997, :322-329
[8]  
Chen D., 2011, Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, p26:1
[9]  
DALLY WJ, 1987, IEEE T COMPUT, V36, P547, DOI 10.1109/TC.1987.1676939
[10]  
Dongarra J., 2013, REPORT VISIT NATL U