3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

被引:73
作者
Then, Han Wui [1 ]
Dasgupta, S. [1 ]
Radosavljevic, M. [1 ]
Agababov, P. [1 ]
Ban, I. [1 ]
Bristol, R. [1 ]
Chandhok, M. [1 ]
Chouksey, S. [1 ]
Holybee, B. [1 ]
Huang, C. Y. [1 ]
Krist, B. [1 ]
Jun, K. [1 ]
Lin, K. [1 ]
Nidhi, N. [1 ]
Michaelos, T. [1 ]
Mueller, B. [1 ]
Paul, R. [1 ]
Peck, J. [1 ]
Rachmady, W. [1 ]
Staines, D. [1 ]
Talukdar, T. [1 ]
Thomas, N. [1 ]
Tronic, T. [1 ]
Fischer, P. [1 ]
Hafez, Walid [1 ]
机构
[1] Intel Corp, Components Res, Technol Dev Grp, Hillsboro, OR 97124 USA
来源
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年
关键词
DEVICES;
D O I
10.1109/iedm19573.2019.8993583
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have demonstrated industry's first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric metal gate enhancement-mode (e-mode) GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 300mm 3D layer transfer. The fabricated (bottom device layer) high-K dielectric e-mode GaN NMOS transistors, integrated on a 300mm HR Si(111) substrate, show excellent electrical characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact voltage regulators and RF front-end components such as power amplifiers, low-noise amplifiers and RF switches, with (i) I-OFF as low as 100pA/mu m (V-D=5V, V-G=0V), (ii) high I-D,I-max=1.5mA/mu m; (iii) R-ON as low as 610 Omega-mu m, significantly better than industry-standard Si transistors at equivalent drain breakdown (BVD), (iv) excellent RF performance: f(T)=190GHz, f(MAX)=300GHz, PAE=56% at mmwave frequency (f=28GHz), and PAE=70% at sub-7GHz (f=5GHz), significantly better than industry-standard GaAs and Si RF transistors, (v) excellent RF switch FOM, RonCoff=110fs, and (vi) low noise figure, NFmin=1.36dB (f=28GHz), 0.4dB (f=5GHz) and 0.27dB (f=1.8GHz), all at SoC-compatible voltages. The fabricated (top device layer) L-G=65nm and 130nm Si PMOS transistors, which are monolithically integrated on top of the bottom GaN NMOS transistors by 300mm 3D layer transfer, show respectively, high drive current of 0.85mA/mu m, and low I-off of 150pA/mu m at V-D=-1.2V. Such a monolithic 3D integration of GaN NMOS and Si PMOS enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory functions and analog circuitries for next generation power delivery, RF (5G and beyond) and SoC applications.
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页数:4
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