A two-stage reconfigurable image processing system

被引：0

作者：

Deng, YX ^{[1
]}

Hwang, CJ ^{[1
]}

Lou, DC ^{[1
]}

机构：

[1] Yuan Ze Univ, Dept Comp Engn & Sci, Chungli 320, Taiwan

来源：

ISSPA 2005: The 8th International Symposium on Signal Processing and its Applications, Vols 1 and 2, Proceedings | 2005年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Digital image processing needs complex computation that is time-consuming. The computations are computed by software usually, but to speed up the computation is necessary for real-time systems. However, a high performance processor means high cost and hard to implement. To solve the problem, most systems utilize one processor with some digital image co-processors to replace software programming but the disadvantage is inflexibility. If the method of image processing changes then to modify or redesign the hardware is necessary. In this article, a new method based on two-stage reconfigurable computing system (TSRCS) architecture is proposed to achieve a flexible design for image processing system. The TSRCS splits the reconfiguration scheme into two stages and takes advantage of this architecture to recombine any image processing systems. An application is also implemented and successfully verified the adaptability of image processing system based on the TSRCS architecture.

引用

页码：315 / 318

页数：4