A new design partitioning approach for low power high-level synthesis

被引：0
|
作者：
Rettberg, A [1 ]
Rammig, FJ
机构：
[1] Paderborn Univ, C LAB, Paderborn, Germany
[2] Paderborn Univ, Heinz Nixdorf Inst, Paderborn, Germany
来源：
DELTA 2006: THIRD IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The optimization of power consumption at a very high design level is a critical step towards a power-efficient digital system design. The increasing usage of battery-powered and often wireless portable systems is driving the demand for IC and SoC devices consuming the smallest possible amount of power. The aim of the method presented in this paper is to integrate low power methods within the scheduling process of the High-Level Synthesis by defining partitions. Starting from an Controlled-Data-Flow-Graph (CDFG) the proposed method uses standard scheduling techniques and path analysis on the graph to identify regions that can be combined to partitions. Each partition has a controlled activation or deactivation mechanism. That mean, the partition can be switched off when it is not used. As an example design, a part of the MPEG-2 algorithm is used.
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页码：143 / +
页数：2
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