A Novel High-Speed Low-Power Binary Signed-Digit Adder

被引：0

作者：

Timarchi, Somayeh ^{[1
]}

Ghayour, Parham ^{[1
]}

Shahbahrami, Asadollah ^{[2
]}

机构：

[1] Shahid Beheshti Univ, Dept Elect & Comp Engn, Tehran, Iran

[2] Univ Guilan, Dept Comp Engn, Rasht, Iran

来源：

2012 16TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS) | 2012年

关键词：

Redundant addition; binary signed digit number system; high-speed low-power arithmetic; FPGA; VLSI;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Addition is one of the most important arithmetic operations in digital computation. Optimization of adders' speed, power, and area is a challenging task. To this end, redundant number system has been proposed in the literatures. In this paper, we propose a new redundant binary signed-digit adder that not only utilizes specific encoding for the input operands, but also uses a new efficient adder structure. Using this technique we can generate low power signed digit adders that perform fast additions. The comparisons show delay, power and area reduction both on FPGA and Synopsys Design Vision tool.

引用

页码：70 / 74

页数：5

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