Non-idealities in linear CDR phase detectors

被引：4

作者：

Cao, Jun ^{[1
]}

Huang, Sui ^{[2
]}

Green, Michael M. ^{[2
]}

机构：

[1] Broadcom Corp, Irvine, CA 92618 USA

[2] Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA

来源：

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | 2013年 / 41卷 / 04期

关键词：

wideband data communication; receiver; analog; CMOS; clock-data recovery (CDR); phase detector; mismatch; delay; phase offset; capture range; jitter tolerance; DATA RECOVERY CIRCUIT; CLOCK RECOVERY; CMOS;

D O I：

10.1002/cta.800

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The effects of circuit non-idealities in a Hogge-type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non-idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop. Lower bounds on the bandwidths of the various blocks in the CDR are also established in order to avoid variations of the transfer characteristics. Copyright (c) 2011 John Wiley & Sons, Ltd.

引用

页码：331 / 346

页数：16

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