Development of Dynamic Reconfiguration Implementation of AES on FPGA Platform

被引:0
作者
Burman, Shuchishman [1 ]
Rangababu, P. [1 ]
Datta, Kamalika [2 ]
机构
[1] Natl Inst Technol Meghalaya, Dept Elect & Commun Engn, Shillong 793003, Meghalaya, India
[2] Natl Inst Technol Meghalaya, Dept Comp Sci & Engn, Shillong 793003, Meghalaya, India
来源
PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC) | 2017年
关键词
AES; Dynamic reconfiguration; FPGA;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Dynamic partial reconfiguration is the ability of modern FPGA's to dynamically change some selected area(s) of the FPGA while rest of the design is running. This feature allows to reuse the same hardware for different applications. In this paper we have chosen various Advanced Encryption Standard (AES) key sizes, viz. 128-bit, 192-bit and 256-bit as parameter for reconfiguration. A dynamic reconfigurable implementation for high speed and low area AES has been developed on Digilent's Zed board (XC7z020CLG484-1). The proposed work implements two pipelined versions of AES for reconfiguration, (i) High speed version using modular pipelining, (ii) Area efficient version using simpler pipeline. Maximum operational frequencies of 389.25, 389.25 & 386.2 MHz have been achieved using modular pipelined approach, while 204.3, 203.7 & 146.5 MHz is obtained for simple pipelined approach corresponding to 128, 192 and 256-bit AES respectively. The obtained throughput ranges from 49.8 Gbps to 98.8 Gbps for modular pipeline, and from 26.15 to 39.11 Gbps for simple pipeline structure.
引用
收藏
页码:247 / 251
页数:5
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