FPGA-Based Parallel Implementation of SURF Algorithm

被引:0
作者
Chen, Wenjie [1 ]
Ding, Shuaishuai [2 ]
Chai, Zhilei [2 ,3 ]
He, Daojing [1 ]
Zhang, Weihua [4 ]
Zhang, Guanhua [1 ]
Peng, Qiwei [5 ]
Luo, Wang [5 ]
机构
[1] East China Normal Univ, MoE Engn Res Ctr Software Hardware Codesign Techn, Shanghai 200062, Peoples R China
[2] Jiangnan Univ, Sch IoT Engn, Wuxi 214122, Peoples R China
[3] State Key Lab Math Engn & Adv Comp, Wuxi 214125, Peoples R China
[4] Fudan Univ, Parallel Proc Inst, Shanghai 200433, Peoples R China
[5] NARI Grp Corp, State Grid Elect Power Res Inst, Nanjing 211000, Jiangsu, Peoples R China
来源
2016 IEEE 22ND INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS) | 2016年
基金
国家高技术研究发展计划(863计划);
关键词
SURF; FPGA; parallel computing; High Level Synthesis;
D O I
10.1109/ICPADS.2016.47
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
SURF (Speeded up robust features) detection is used extensively in object detection, tracking and matching. However, due to its high complexity, it is usually a challenge to perform such detection in real time on a general-purpose processor. This paper proposes a parallel computing algorithm for the fast computation of SURF, which is specially designed for FPGAs. By efficiently exploiting the advantages of the architecture of an FPGA, and by appropriately handling the inherent parallelism of the SURF computation, the proposed algorithm is able to significantly reduce the computation time. Our experimental results show that, for an image with a resolution of 640x480, the processing time for computing using SURF is only 0.047 seconds on an FPGA (XC6SLX150T, 66.7 MHz), which is 13 times faster than when performed on a typical i3-3240 CPU (with a 3.4 GHz main frequency) and 249 times faster than when performed on a traditional ARM system (CortexTM-A8, 1 GHz).
引用
收藏
页码:308 / 315
页数:8
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