Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

被引：6

作者：

Huang, Li-Ren ^{[1
]}

Huang, Shi-Yu ^{[1
]}

Tsai, Kun-Han ^{[2
]}

Cheng, Wu-Tung ^{[2
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[2] Mentor Graph Corp, Silicon Test Solut Div, Wilsonville, OR 97070 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2014年 / 33卷 / 03期

关键词：

2.5-D stacked integrated circuit (IC); delay characterization; delay testing; interposer wire; post-bond IC; resistive bridging fault; DELAY;

D O I：

10.1109/TCAD.2013.2290589

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, our method can also be used to characterize the propagation delay across each fault-free interposer wire.

引用

页码：476 / 488

页数：13