Modeling of Coupled TSVs in 3D ICs

被引:0
作者
Engin, A. Ege [1 ]
Raghavan, Srinidhi N. [1 ]
机构
[1] San Diego State Univ, Dept Elect & Comp Engn, San Diego, CA 92182 USA
来源
2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC) | 2012年
关键词
THROUGH-SILICON; DESIGN;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents analytical formulas to extract an equivalent circuit model for coupled through silicon via (TSV) structures in a 3D integrated circuit. We make use of a multiconductor transmission line approach to model coupled TSV structures. TSVs are embedded in a lossy silicon medium, hence they behave as metal-insulator-semiconductor (MIS) transmission lines. The models we present can accurately capture the transition between slow-wave and dielectric quasi-TEM modes, which are characteristic for MIS transmission lines, as well as the metal-oxide- semiconductor (MOS) varactor capacitance. The results are validated against 2D quasi-static simulations and 3D full-wave electromagnetic simulations. The derived equivalent circuit models can easily be applied in circuit simulators to analyze crosstalk behavior of TSVs in a 3D integrated system.
引用
收藏
页码:7 / 11
页数:5
相关论文
共 15 条
[1]  
[Anonymous], P EMPC RIM IT JUN
[2]  
[Anonymous], ANS HFSS V1 3 0
[3]   Design challenges of technology scaling [J].
Borkar, S .
IEEE MICRO, 1999, 19 (04) :23-29
[4]  
Hu G., 2007, INTEL TECHNOLOGY J, V11
[5]   Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies [J].
Khan, Nauman H. ;
Alam, Syed M. ;
Hassoun, Soha .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (04) :647-658
[6]  
Little M. J., 1989, Proceedings: International Conference on Wafer Scale Integration (IEEE Cat. No.89CH2680-7), P55, DOI 10.1109/WAFER.1989.47536
[7]   Through-Silicon Via (TSV) [J].
Motoyoshi, Makoto .
PROCEEDINGS OF THE IEEE, 2009, 97 (01) :43-48
[8]  
Paul C., 1976, TECH REP
[9]  
Paul C. R., 2007, ANAL MULTICONDUCTOR