Methodologies and algorithms for testing switch-based NoC interconnects

被引：22
作者：
Grecu, C [1 ]
Pande, P [1 ]
Wang, BS [1 ]
Ivanov, A [1 ]
Saleh, R [1 ]
机构：
[1] Univ British Columbia, Dept Elect & Comp Engn, SoC Res Lab, Vancouver, BC V6T 1Z4, Canada
来源：
DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS | 2005年
关键词：
D O I：
10.1109/DFTVS.2005.45
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.
引用
收藏
页码：238 / 246
页数：9
相关论文
共 20 条
[11]  
MARINISSEN EJ, P ITC 1998, P284
[12]   Indirect test architecture for SoC testing [J].
Nahvi, M ;
Ivanov, A .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (07) :1128-1142
[13]   Switch-based interconnect architecture for future systems on chip [J].
Pande, PP ;
Grecu, C ;
Ivanov, A ;
Saleh, R .
VLSI CIRCUITS AND SYSTEMS, 2003, 5117 :228-237
[14]  
Pande PP, 2003, PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, P217
[15]  
STUNKEL CB, 1997, P 24 ACM INT S COMP
[16]  
VANDEGOOR AJ, 1995, EUR CONF DESIG AUTOM, P133, DOI 10.1109/EDTC.1995.470408
[17]  
VARATKAR G, 2004, IEEE T VLSI, V12
[18]   Bringing communication networks on a chip: Test and verification implications [J].
Vermeulen, B ;
Dielissen, J ;
Goossens, K ;
Ciordas, C .
IEEE COMMUNICATIONS MAGAZINE, 2003, 41 (09) :74-81
[19]  
Wang BS, 2004, 19TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, P120
[20]   Testing embedded-core-based system chips [J].
Zorian, Y ;
Marinissen, EJ ;
Dey, S .
COMPUTER, 1999, 32 (06) :52-+
12