Methodologies and algorithms for testing switch-based NoC interconnects

被引：22
作者：
Grecu, C [1 ]
Pande, P [1 ]
Wang, BS [1 ]
Ivanov, A [1 ]
Saleh, R [1 ]
机构：
[1] Univ British Columbia, Dept Elect & Comp Engn, SoC Res Lab, Vancouver, BC V6T 1Z4, Canada
来源：
DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS | 2005年
关键词：
D O I：
10.1109/DFTVS.2005.45
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.
引用
收藏
页码：238 / 246
页数：9
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